A memory cell array is an important component in modern digital systems, and is often a bottleneck of power consumption in system design. As the demand for portable devices increases in the market, the requirement for technologies to reduce the power consumption of memory cell arrays becomes higher and higher. Sub-threshold design is a focus in extremely low power design nowadays. By reducing the supply voltage (Vdd) entering into the sub-threshold area of the circuit—Vdd lower than the threshold voltage (Vth), the system can operate in the linear range of the circuit, and thereby the dynamic and static power consumption of the system can be reduced significantly. The design of sub-threshold memory cell arrays further highlights the advantage of sub-threshold design in low-power consumption. However, in the actual implementation process, the design introduces a series of problems: 1) the power-up current/shutdown current ratio (Ion/Ioff) is low—in conventional designs, the power-up current/shutdown current ratio (Ion/Ioff) is approximately 107, whereas in sub-threshold design, the Ion/Ioff ratio is only 103-104; 2) the number of memory cells that can be connected in series on a bit line is limited, and therefore the capacity of a memory cell array is limited, and the area consumption is high; 3) in the read cycle, the oscillation amplitude of a bit line is low, and the detection tolerance of a sensitive amplifier is low; 4) the performance is susceptible to process deviations, etc. The key point in the problem is that the effect of drain current in the matching transistors for unselected logical memory cells on the bit line in the sub-threshold area is much more severe than the effect in the super-threshold area under the corresponding conditions. In addition, the effect will be further aggravated if there are process deviations. If there is not enough redundancy (the number of memory cells connected in series on the bit line is greater than a threshold), the power-up current of a selected memory cell may be interfered by the drain current accumulated in the unselected memory cells; as a consequence, the circuit can't recognize the correct logic subsequently, which will result in read and write failure of the memory cell (FIG. 1). In view of the process deviations and the bias voltage of the follow-up sensitive amplifier, the number of memory cells on a bit line will be further limited. At present, there are two trends in the design of sub-threshold memory cell arrays: 1) calculate the proportional relation of Ion/Ioff of the transistors within different process corners, and control the number of memory cells on the same bit line strictly; 2) introduce drain current compensation logic in the memory cell. However, the memory cell arrays are high-capacity logical units and have high requirements for design density. Both methods described above can't effectively solve the problem of large chip area consumption of memory cell array.